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philips semiconductors pca9560 dual 5-bit multiplexed 1-bit latched i 2 c eeprom dip switch product data sheet supersedes data of 2003 jun 27 2004 may 19 integrated circuits
philips semiconductors product data sheet pca9560 dual 5-bit multiplexed 1-bit latched i 2 c eeprom dip switch 2 2004 may 19 features ? 5-bit 3-to-1 multiplexer, 1-bit latch dip switch ? 5-bit external hardware pins ? two 6-bit internal non-volatile registers, fully pin-to-pin compatible with pca9559 ? selection between the two non-volatile registers ? selection between non-volatile registers and external hardware pins ? i 2 c/smbus interface logic ? internal pull-up resistors on input pin and control signals ? active high write protect on input controls the ability to write to the non-volatile registers ? 2 address pins, allowing up to 4 devices on the i 2 c-bus ? 5 open drain multiplexed outputs ? open drain non-multiplexed output ? internal 6-bit non-volatile registers programmable and readable via i 2 c-bus ? external hardware 5-bit value r eadable via i 2 c-bus ? multiplexer selection can be overridden by i 2 c-bus ? operating power supply voltage 3.0 v to 3.6 v ? 5 v and 2.5 v tolerant inputs/outputs ? 0 to 400 khz clock frequency ? esd protection exceeds 2000 v hbm per jesd22-a114, 200 v mm per jesd22-a115, and 1000 v cdm per jesd22-c101 ? latch-up testing is done to jesdec standard jesd78 which exceeds 100 ma. ? package offering: so20, tssop20 description the pca9560 is a 20-pin cmos device consisting of two 6-bit non-volatile eeprom registers, 5 hardware pin inputs and a 5-bit multiplexed output with one latched eeprom bit. it is used for dip switch-free or jumper-less system configuration and supports mobile and desktop vid configuration, where 3 preset values (2 sets of internal non-volatile registers and 1 set of external hardware pins) set processor voltage for operation in either performance, deep sleep or deeper sleep modes. the pca9560 is also useful in server and telecom/networking applications when used to replace dip switches or jumpers, since the settings can be easily changed via i 2 c/smbus without having to power down the equipment to open the cabinet. the non-volatile memory retains the most current setting selected before the power is turned off. the pca9560 typically resides between the cpu and voltage regulator module (vrm) when used for cpu vid (voltage identification code) configuration. it is used to bypass the cpu-defined vid values and provide a different set of vid values to the vrm, if an increase in the cpu voltage is desired. an increase in cpu voltage combined with an increase in cpu frequency leads to a performance boost of up to 7.5%. lower cpu voltage reduces power consumption. the main advantage of the pca9560 over the older pca9559 device in this application is that it contains two internal non-volatile eeprom registers instead of just one, allowing three independent settings (performance operation, deep sleep mode and deeper sleep mode) instead of only two (performance operation and deep sleep mode). the pca9560 is footprint compatible and a drop-in replacement for the pca9559, without any software modifications required. the pca9560 has 2 address pins allow up to 4 devices to be placed on the same i 2 c bus or smbus. pin configuration scl sda mux_in b v dd 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 mux_in c mux_in d mux_in e mux_out b mux_out c mux_out d mux_out e sw00829 gnd 9 10 a1 a0 12 11 non-muxed_out mux_out a mux_in a wp mux_select_1 mux_select_0 figure 1. pin configuration pin description pin symbol function 1 scl serial i 2 c-bus clock 2 sda serial bi-directional i 2 c-bus data 3 a1 programmable lsbs of i 2 c 4 a0 g address 59 mux_in ae external inputs to multiplexer 10 gnd ground 11 mux_ select_0 selects mux_in inputs or register contents for mux_out outputs 1216 mux_out ea open drain multiplexed outputs 17 non-muxed_ output open drain output from non-volatile memory 18 mux_ select_1 selects between the two non-volatile registers 19 wp active high non-volatile register write-protect input 20 v dd power supply: +3.0 to +3.6 v ordering information packages temperature range order code topside mark drawing number 20-pin plastic so 40 to +85 c PCA9560D PCA9560D sot163-1 20-pin plastic tssop 40 to +85 c pca9560pw pca9560 sot360-1 standard packing quantities and other packaging data are available at www.philipslogic.com/packaging.
philips semiconductors product data sheet pca9560 dual 5-bit multiplexed 1-bit latched i 2 c eeprom dip switch 2004 may 19 3 block diagram mux_out_a mux_out_b mux_out_c mux_out_d mux_out_e mux_in_a mux_in_b mux_in_c mux_in_d mux_in_e non-volatile register 0 6-bit eeprom non-volatile register 1 6-bit eeprom select logic write protect mux_select_1 mux_select_0 6 6 3 5 5 non-muxed_out 8 a0 a1 sw00841 pca9560 i 2 c/smbus control logic 6-bit 2 to 1 demultiplexer 5-bit 2 to 1 demultiplexer sda scl v dd gnd input filter power-on reset latch nmo figure 2. block diagram
philips semiconductors product data sheet pca9560 dual 5-bit multiplexed 1-bit latched i 2 c eeprom dip switch 2004 may 19 4 device address following a start condition the bus master must output the address of the slave it is accessing. the address of the pca9560 is shown in figure 3. to conserve power, no internal pull-up resistors are incorporated on the hardware selectable address pins and they must be pulled high or low. the last bit of the slave address byte defines the operation to be performed. when set to logic 1 a read is selected while a logic 0 selects a write operation. 0 0 1 a1 a0 r/w 11 sw00955 msb lsb fixed programmable figure 3. slave address control register following the successful acknowledgement of the slave address, the bus master will send a byte to the pca9560, which will be stored in the control register. this register can be written and read via the i 2 c-bus. sw00954 d7 d6 d5 d4 d3 d2 d1 d0 figure 4. control register control register definition following the address and acknowledge bit with logic 0 in the read/write bit, the first byte written is the command byte. if th e command byte is reserved and therefore not valid, it will not be acknowledged. only valid command bytes will be acknowledged. table 1. register addresses d7 d6 d5 d4 d3 d2 d1 d0 register name type register function 0 0 0 0 0 0 0 0 eeprom 0 read/write eeprom byte 0 register 0 0 0 0 0 0 0 1 eeprom 1 read/write eeprom byte 1 register 1 1 1 1 1 1 1 1 mux_in read mux_in values register table 2. commands d7 d6 d5 d4 d3 d2 d1 d0 command 1 1 1 1 1 0 0 0 mux_out from eeprom byte 0 1 1 1 1 1 1 0 0 mux_out from eeprom byte 1 1 1 1 1 1 x 1 0 mux_out from mux_in 1 1 1 1 1 x x 1 mux_out from mux_select 2 note: 1. all other combinations are reserved. 2. mux_select pins select between mux_in and eeprom to mux_out.
philips semiconductors product data sheet pca9560 dual 5-bit multiplexed 1-bit latched i 2 c eeprom dip switch 2004 may 19 5 register description if the command byte is an eeprom address, the next byte sent will be programmed into that eeprom address on the following stop condition, if the wp is logic 0. if more than one byte is sent sequentially, the second byte will be written in the other-volat ile register, on the following stop condition. if any more data bytes are sent after the second byte, they will not be acknowledged and no bytes wil l be written to the non-volatile registers. after a byte is read from or written to the eeprom, the part automatically points to the next non-v olatile register. if the command code was ffh, the mux_in values are sent with the three msbs padded with zeroes as shown below. if the command codes wa s 00h, then the non-volatile register 1 is sent, and if the command code was 01h, then the non-volatile register 1 is sent. eeprom byte 0 register d7 d6 d5 d4 d3 d2 d1 d0 write x x non-muxed data eeprom 0 data e eeprom 0 data d eeprom 0 data c eeprom 0 data b eeprom 0 data a read 0 0 non-muxed data eeprom 0 data e eeprom 0 data d eeprom 0 data c eeprom 0 data b eeprom 0 data a default 0 0 0 0 0 0 0 0 eeprom byte 1 register d7 d6 d5 d4 d3 d2 d1 d0 write x x non-muxed data eeprom 1 data e eeprom 1 data d eeprom 1 data c eeprom 1 data b eeprom 1 data a read 0 0 non-muxed data eeprom 1 data e eeprom 1 data d eeprom 1 data c eeprom 1 data b eeprom 1 data a default 0 0 0 0 0 0 0 0 mux_in register d7 d6 d5 d4 d3 d2 d1 d0 read 0 0 0 mux_in data e mux_in data d mux_in data c mux_in data b mux_in data a if the command byte is a mux command byte, any additional data bytes sent after the mux command code will not be acknowledged. if the read/write bit in the address is a logic 1, then a read operation follows and the data sent out depends on the previously store d command code. the mux_select_1 pin can function as the over-ride pin as on the pca9559 if the non-volatile register 1 is left at all 0s. the non_muxed_out pin is a latched output. it is latched when mux_select_0 = 1. it is transparent when the mux_select_0 = 0. th e data sent out on the non_muxed_out output is the 6th most significant bit of the non-volatile register. whether this comes from the non-volatile register 0 or non-volatile register 1 depends on the command code or the external mux-select pins. after a valid i 2 c write operation to the eeprom, the part cannot be addressed via the i 2 c for 3.6 ms. if the part is addressed prior to this time, the part will not acknowledge its address. note: 1. to ensure data integrity, the non-volatile register must be internally write protected when v dd to the i 2 c bus is powered down or v dd to the component is dropped below normal operating levels.
philips semiconductors product data sheet pca9560 dual 5-bit multiplexed 1-bit latched i 2 c eeprom dip switch 2004 may 19 6 conversion from the pca9559 to the pca9560 the pca9560 is a drop in replacement to the pca9559 with no software modifications. the pca9559 has only one mux_select pin to choose between the mux_in values and the single non-volatile register. since the pca9560 has two internal non-volatile register s, if register 1 is left to all 0's (default condition) then the mux_select_1 pin can function the same as the pca9559 override # pin and mux_se lect_0 pin can function the same as the pca9559 mux_in pin. the pca9560 can read the mux_in_x values via i 2 c that the paca9559 cannot do. another difference is that the mux_select_x control pins can be overridden by i 2 c. to replace the pca9559 with the pca9560, the function table for the mux_out outputs and the non_muxed_out output must stay the same and the mux_select pin functions should not be overridden by i 2 c. external control signals the write protect (wp) input is used to control the ability to write the content of the non-volatile registers. if the wp signa l is logic 0, the i 2 c bus will be able to write the contents of the non-volatile registers. if the wp signal is logic 1, data will not be allowed to be w ritten into the non-volatile registers. in this case, the slave address and the command code will be acknowledged but the following data bytes will not be acknowledged and the eeprom is not updated. the factory default for the contents of the non-volatile register are all logic 0. these stored values can be read or written u sing the i 2 c-bus (described in the next section). the wp, mux_in*, mux_select_0, and mux_select_1 signals have internal pull-up resistors. see the dc and ac characteristics for hysteresis and signal spike suppression figures. function table 1 wp mux_select_0 mux_select_1 commands 0 x x write to the non-volatile registers through i 2 c bus allowed 1 x x write to the non-volatile registers through i 2 c bus not allowed x 0 1 mux_out and non_muxed_out (transparent) from eeprom byte 0 x 0 0 mux_out and non_muxed_out (transparent) from eeprom byte 1 x 1 1 mux_out from mux_in inputs and non_muxed_out latched (from eeprom 0) x 1 0 mux_out from mux_in inputs and non_muxed_out latched (from eeprom 1) note: 1. this table is valid when not overridden by i 2 c control register. power-on reset (por) when power is applied to v dd , an internal power-on reset holds the pca9560 in a reset state until v dd has reached v por . at that point, the reset condition is released and the pca9560 volatile registers and i 2 c/smbus state machine will initialize to their default states. the mux_out and non_muxed_out pin values depend on: the mux_select_0 and mux_select_1 logic levels, selecting either the mux_in input pins or one of the two 6-bit eeproms the previously stored values in the eeprom registers/current mux_in pin values as shown in the function table
philips semiconductors product data sheet pca9560 dual 5-bit multiplexed 1-bit latched i 2 c eeprom dip switch 2004 may 19 7 characteristics of the i 2 c-bus the i 2 c-bus is for 2-way, 2-line communication between different ics or modules. the two lines are a serial data line (sda) and a ser ial clock line (scl). both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device . data transfer may be initiated only when the bus is not busy. bit transfer one data bit is transferred during each clock pulse. the data on the sda line must remain stable during the high period of the clock pulse as changes in the data line at this time will be interpreted as control signals (see figure 5). sda scl sw00363 data line stable; data valid change of data allowed figure 5. bit transfer start and stop conditions both data and clock lines remain high when the bus is not busy. a high-to-low transition of the data line, while the clock is h igh is defined as the start condition (s). a low-to-high transition of the data line while the clock is high is defined as the stop condition (p) (see figure 6). system configuration a device generating a message is a `transmitter', a device receiving is the `receiver'. the device initiates a transfer is the `master' and the devices which are controlled by the master are the `slaves' (see figure 7). sda scl sw00365 s p sda scl start condition stop condition figure 6. definition of start and stop conditions master transmitter/ receiver slave receiver slave transmitter/ receiver master transmitter master transmitter/ receiver sda scl sw00366 i 2 c multiplexer slave figure 7. system configuration
philips semiconductors product data sheet pca9560 dual 5-bit multiplexed 1-bit latched i 2 c eeprom dip switch 2004 may 19 8 acknowledge the number of data bytes transferred between the start and the stop conditions from transmitter to receiver is not limited. eac h byte of eight bits is followed by one acknowledge bit. the acknowledge bit is a high-level put on the bus by the transmitter whereas the master ge nerates an extra acknowledge related clock pulse. a slave receiver which is addressed must generate an acknowledge after the reception of each byte. also a master must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. the device that acknowledges h as to pull down the sda line during the acknowledge clock pulse, so that the sda line is stable low during the high period of the acknowledge r elated clock pulse, set-up and hold times must be taken into account. a receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocke d out of the slave. in this event, the transmitter must leave the data line high to enable the master to generate a stop condition. data output by transmitter scl from master sw00368 data output by receiver 12 89 s start condition clock pulse for acknowledgement acknowledge not acknowledge figure 8. acknowledgement on the i 2 c-bus
philips semiconductors product data sheet pca9560 dual 5-bit multiplexed 1-bit latched i 2 c eeprom dip switch 2004 may 19 9 bus transactions data is transmitted to the pca9560 registers using write byte transfers (see figures 9 and 10). data is read from the pca9560 r egisters using read and receive byte transfers (see figure 11). d5 d4 d3 d2 d1 x x 0 1 1 a1 a0 1 0 s0a a a r/w d0 slave address eeprom byte 0 data sw00956 0000000 0 p stop condition control register write on eeprom byte 0 acknowledge from slave acknowledge from slave acknowledge from slave start condition figure 9. write on 1 eeprom e assuming wp = 0 d4 d3 d2 d1 d0 d5 d4 d3 d2 d1 d0 x d5 0 1 1 a1 a0 1 0 s0a a x r/w p x sw00957 a slave address stop condition start condition 00000000 xa acknowledge from slave acknowledge from slave control register write on eeprom byte 0 eeprom byte 0 data eeprom byte 1 data figure 10. write on 2 eeproms e assuming wp = 0 sw00958 slave address no acknowledge from master 4 3 2 1 0 0 0 1 1 a1 a0 1 0 0 1 1 a1 a0 1 0 s0a a 0 r/w p s a slave address stop condition start condition 11111 11 1 0 na acknowledge from master control register read mux_in values data from mux_in acknowledge from master acknowledge from master 1 r/w restart figure 11. read mux_in register
philips semiconductors product data sheet pca9560 dual 5-bit multiplexed 1-bit latched i 2 c eeprom dip switch 2004 may 19 10 absolute maximum ratings 1, 2 in accordance with the absolute maximum rating system (iec 134) voltages are referenced to gnd (ground = 0 v) symbol parameter conditions rating unit v dd dc supply voltage 0.5 to +4.0 v v in dc input voltage note 3 0.5 to +5.5 v v out dc output voltage note 3 0.5 to +5.5 v t stg storage temperature range 60 to +150 c notes: 1. stresses beyond those listed may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under arecommended operating conditionso is not implied. exposur e to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. the performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create ju nction temperatures which are detrimental to reliability. the maximum junction temperature of this integrated circuit should not excee d 150 c. 3. the maximum input or output voltage is the lesser of 5.5 v or v dd + 4.0 v, except for very short (e.g., system start-up or shut-down) durations. recommended operating conditions symbol parameter conditions limits unit symbol parameter conditions min max unit v dd dc supply voltage e 3.0 3.6 v v il low-level input voltage scl, sda i ol = 3 ma 0.5 0.9 v v ih high-level input voltage scl, sda i ol = 3 ma 2.7 5.5 1 v v o low level out p ut voltage scl sda i ol = 3 ma e 0.4 v v ol low - le v el o u tp u t v oltage scl , sda i ol = 6 ma e 0.6 v v il low-level input voltage mux_in, mux_select_0, mux_select_1 e 0.5 0.8 v v ih high-level input voltage mux_in, mux_select_0, mux_select_1 e 2.0 5.5 1 v i ol low-level output current mux_out, non_muxed_out e e 8 ma i oh high-level output current mux_out, non_muxed_out e e 100 m a dt/dv input transition rise or fall time dt/dv e 0 10 ns/v t amb operating ambient temperature t amb e 40 85 c notes: 1. the maximum input voltage is the lesser of 5.5 v or v dd + 4.0 v, except for very short (e.g., system start-up or shut-down) durations.
philips semiconductors product data sheet pca9560 dual 5-bit multiplexed 1-bit latched i 2 c eeprom dip switch 2004 may 19 11 dc characteristics symbol parameter test condition limits unit symbol parameter test condition min. typ. max. unit supply v dd supply voltage 3 e 3.6 v i ddl supply current operating mode all inputs = 0 v e e 1 ma i ddh supply current operating mode all inputs = v dd e e 600 m a v por power-on reset voltage no load; v i = v dd or gnd e 2.3 2.7 v input scl: input/output sda v il low-level input voltage 0.5 e 0.8 v v ih high-level input voltage 2 e 5.5 1 v i ol low-level output current v ol = 0.4 v 3 e e ma i ol low-level output current v ol = 0.6 v 6 e e ma i ih leakage current high v i = v dd 1 e 1 m a i il input current low v i = gnd 1 e 1 m a c i input capacitance e 3 6 pf wp, mux_select_0, mux_select_1 i ih leakage current high v i = v dd 1 e 1 m a i il input current low v dd = 3.6 v; v i = gnd 20 e 50 m a c i input capacitance e 2.5 5 pf mux_in a e i ih leakage current high v i = v dd 1 e 1 m a i il input current low v dd = 3.6 v; v i = gnd 20 e 50 m a c i input capacitance e 2.5 5 pf a0, a1 inputs i ih leakage current high v i = v dd 1 e 1 m a i il input current low v dd = 3.6 v; v i = gnd 20 e 50 m a c i input capacitance e 2 4 pf mux_out v ol low-level output voltage i ol = 100 m a e e 0.4 v v ol low-level output voltage i ol = 4 ma e e 0.7 v i oh high-level output current v oh = v dd e e 100 m a non-muxed_out v ol low-level output voltage i ol = 100 m a e e 0.4 v v ol low-level output voltage i ol = 2 ma e e 0.7 v note: 1. the maximum input voltage is the lesser of 5.5 v or v dd + 4.0 v, except for very short (e.g., system start-up or shut-down) durations. non-volatile storage specifications parameter specification memory cell data retention 10 years min number of memory cell write cycles 100,000 cycles min application note an250 i 2 c dip switch provides additional information on memory cell data retention and the minimum number of write cycles.
philips semiconductors product data sheet pca9560 dual 5-bit multiplexed 1-bit latched i 2 c eeprom dip switch 2004 may 19 12 sac characteristics symbol parameter limits unit symbol parameter min. typ. max. unit mux_in ? mux_out t plh low-to-high transition time e 28 40 ns t phl high-to-low transition time e 8 15 ns select ? mux_out t plh low-to-high transition time e 30 43 ns t phl high-to-low transition time e 10 15 ns t r output rise time 1.0 e 3 ns/v t f output fall time 1.0 e 3 ns/v c l test load capacitance on outputs e e 50 pf select ? non-muxed_out t plh low-to-high transition time e 30 40 ns t phl high-to-low transition time e 9 15 ns ac specifications symbol parameter standard mode i 2 c-bus fast mode i 2 c-bus units min max min max f scl operating frequency 0 100 0 400 khz t buf bus free time between stop and start conditions 4.7 e 1.3 e m s t hd;sta hold time after (repeated) start condition 4.0 e 0.6 e m s t su;sta repeated start condition setup time 4.7 e 0.6 e m s t su;sto set-up time for stop condition 4.0 e 0.6 e m s t hd;dat data in hold time 0 e 0 e ns t vd;ack valid time for ack condition 2 0.3 3.45 0.1 0.9 m s t vd;dat data out valid time 3 300 e 50 e ns t su;dat data set-up time 250 e 100 e ns t low clock low period 4.7 e 1.3 e m s t high clock high period 4.0 e 0.6 e m s t f clock/data fall time e 300 20 + 0.1 c b 1 300 ns t r clock/data rise time e 1000 20 + 0.1 c b 1 300 ns t sp pulse width of spikes that must be suppressed by the input filters e 50 e 50 ns notes: 1. c b = total capacitance of one bus line in pf. 2. t vd;ack = time for acknowledgement signal from scl low to sda (out) low. 3. t vd;dat = minimum time for sda data out to be valid following scl low.
philips semiconductors product data sheet pca9560 dual 5-bit multiplexed 1-bit latched i 2 c eeprom dip switch 2004 may 19 13 t sp t buf t hd;sta p p s t low t r t hd;dat t f t high t su;dat t su;sta sr t hd;sta t su;sto sda scl su00645 figure 12. definition of timing mux input v m v m v m mux output v ol t phl t plz v ol + 0.3 v sw00500 v o figure 13. open drain output enable and disable times definitions r l = load resistor; 1 k w c l = load capacitance includes jig and probe capacitance; 10 pf r t = termination resistance should be equal to z out of pulse generators. pulse generator v in d.u.t. v out c l v cc r l test circuit for open drain outputs r t sw00510 v o figure 14. test circuit
philips semiconductors product data sheet pca9560 dual 5-bit multiplexed 1-bit latched i 2 c eeprom dip switch 2004 may 19 14 so20: plastic small outline package; 20 leads; body width 7.5 mm sot163-1
philips semiconductors product data sheet pca9560 dual 5-bit multiplexed 1-bit latched i 2 c eeprom dip switch 2004 may 19 15 tssop20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm sot360-1
philips semiconductors product data sheet pca9560 dual 5-bit multiplexed 1-bit latched i 2 c eeprom dip switch 2004 may 19 16 revision history rev date description _4 20040519 product data sheet (9397 750 13154). supersedes data of 2003 jun 27 (9397 750 11676). modifications: ? features section, 16 th bullet: from ainputso to ainputs/outputso ? absolute maximum ratings table: v dd , v in , and v out limits modified. note 3 re-written. ? recommended operating conditions v ih max. (on scl, sda) changed from 4.0 v to 5.5 v (with note 1 added). v ih max. (on mux_in, mux_select_0, mux_select_1) changed from 4.0 v to 5.5 v (with note 1 added). ? dc characteristics table: input scl: input/output sda; v ih parameter max. limit modified, and note 1 added. _3 20030627 product data (9397 750 11676); ecn 853-2286 29936 dated 19 may 2003. supersedes data of 2002 may 24 (9397 750 09892). _2 20020524 product data (9397 750 09892); ecn 8532286 28310 of 24 may 2002.
philips semiconductors product data sheet pca9560 dual 5-bit multiplexed 1-bit latched i 2 c eeprom dip switch 2004 may 19 17 purchase of philips i 2 c components conveys a license under the philips' i 2 c patent to use the components in the i 2 c system provided the system conforms to the i 2 c specifications defined by philips. this specification can be ordered using the code 9398 393 40011. definitions short-form specification e the data in a short-form specification is extracted from a full data sheet with the same type number and title. for detailed i nformation see the relevant data sheet or data handbook. limiting values definition e limiting values given are in accordance with the absolute maximum rating system (iec 60134). stress above one or more of the l imiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any o ther conditions above those given in the characteristics sections of the specification is not implied. exposure to limiting values for extended periods may affec t device reliability. application information e applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors ma ke no representation or warranty that such applications will be suitable for the specified use without further testing or modificatio n. disclaimers life support e these products are not designed for use in life support appliances, devices, or systems where malfunction of these products ca n reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use in such applica tions do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes e philips semiconductors reserves the right to make changes in the productseincluding circuits, standard cells, and/or softwaree described or contained herein in order to improve design and/or performance. when the product is in full production (status `production') , relevant changes will be communicated via a customer product/process change notification (cpcn). philips semiconductors assumes no responsibility or liability for th e use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranti es that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. contact information for additional information please visit http://www.semiconductors.philips.com . fax: +31 40 27 24825 for sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com . ? koninklijke philips electronics n.v. 2004 all rights reserved. printed in u.s.a. date of release: 05-04 document order number: 9397 750 13154 philips semiconductors data sheet status [1] objective data sheet preliminary data sheet product data sheet product status [2] [3] development qualification production definitions this data sheet contains data from the objective specification for product development. philips semiconductors reserves the right to change the specification in any manner without notice. this data sheet contains data from the preliminary specification. supplementary data will be published at a later date. philips semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. this data sheet contains data from the product specification. philips semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. relevant changes will be communicated via a customer product/process change notification (cpcn). data sheet status [1] please consult the most recently issued data sheet before initiating or completing a design. [2] the product status of the device(s) described in this data sheet may have changed since this data sheet was published. the l atest information is available on the internet at url http://www.semiconductors.philips.com. [3] for data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. level i ii iii

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